1. Field of the Invention
This invention relates to a low noise complimentary metal oxide semiconductor (CMOS) tri-state output buffer circuit that sequentially activates alternate CMOS devices to reduce peak power supply transients.
Many techniques have been employed to reduce the power and ground current spikes associated with output buffers switching in CMOS circuits. Output buffers are used in order to provide sufficient current drive to switch the large parasitic capacitances associated with both package and printed circuit board interconnects. Low noise outputs are particularly important in a video random access memory (VRAM) integrated circuit (IC), since there are as many as eight outputs switching simultaneously which are asynchronous to the dynamic random access memory (DRAM) timing i.e., serial data outputs (SDQs). Failures caused by power supply noise can occur when the SDQ outputs switch at critical periods in the DRAM timing.